As an Electro Static Discharge (ESD) protection circuit, an RC trigger power clamp MOS is widely used. The RC trigger power clamp MOS has a resistance element and a capacitance element connected between a power supply line and a ground line in series, a CMOS inverter of which an input is connected between the resistance element and the capacitance element, and an N-channel MOSFET as a clamp MOS. A gate of the clamp MOS is connected to an output of the CMOS inverter, and a drain and a source are respectively connected to the power supply line and the ground line.
In the RC trigger power clamp MOS, an input time delay of the CMOS inverter occurs according to a time constant of the resistance element and the capacitance element when an ESD surge current enters the RC trigger power clamp MOS, the output of the CMOS inverter becomes High, and a channel of the clamp MOS is turned ON. Then, the ESD surge current between the drain and the source can be flowed between a power supply and a ground. In a state where the ESD surge current does not enter, a voltage applied to the power supply line turns the output of the CMOS inverter to be Low and turns off the clamp MOS.
In the RC trigger power clamp MOS, the smaller a clamp voltage generated in a protection element is when the ESD surge current enters, the more a voltage applied to an internal circuit can be reduced. Therefore, a smaller clamp voltage index is desired. To reduce the clamp voltage, it is preferable to miniaturize a gate length of the MOS and increase a W size to increase a drive current of the power clamp MOS. However, to miniaturize the gate length and increase the W size cause an off-leak in a normal operation other than an ESD operation. Since the off-leak increases current consumption at the time of circuit standby, the reduction in the clamp voltage and the current consumption have a trade-off relationship.
For example, Patent Document 1 has proposed a structure in which the output of the CMOS inverter is supplied to a gate potential and a well potential of the power clamp MOS as a technology for increasing an ESD discharge capability without increasing an area. By supplying the CMOS inverter output to the well potential and increasing a substrate potential, a parasitic bipolar operation of the power clamp MOS is facilitated, and the ESD discharge capability is increased.